Meeting Abstract
P1.175 Saturday, Jan. 4 15:30 Balancing selection promotes epigenetic variation in prairie vole spatial memory circuit OKHOVAT, M.**; BERRIO, A.*; OPHIR, A.G.*; LYSAK, N.*; PHELPS, S.M.*; Univ. of Texas at Austin, Austin; Univ. of Texas at Austin, Austin; Cornell Univ., Ithaca; Univ. of Florida at Gainesville, Gainesville; Univ. of Texas at Austin, Austin mariam.okhovat@mail.utexas.edu
Evolutionary theory suggests balancing selection should shape the genetic underpinnings of many social behaviors, but few examples exist. Prairie voles are socially monogamous rodents that exhibit a significant degree of extra-pair paternity. Aspects of male mating tactic are regulated by the neuronal expression of vasopressin 1a receptors (V1aR). The retrosplenial cortex (RSC) has been implicated in spatial memory and exhibits highly variable V1aR abundance. Among male prairie voles, RSC-V1aR predicts differences in space use and sexual fidelity. Males with high RSC-V1aR form exclusive home-ranges and mate exclusively within a pair, while those with low RSC-V1aR intrude often and engage in extra-pair fertilizations. To characterize the genetic correlates of this neuronal and behavioral variation, we sequenced ~1kb of coding sequence and ~7kb of non-coding sequence from 40 lab-reared and 30 wild-caught prairie voles. We found two intron SNPs and one 5’ SNP that strongly predicted RSC expression in both populations (P<0.001). Interestingly, the high-expressing allele was associated with fewer CpG sites, and lab-reared animals exhibited a significantly stronger influence of genotype than did wild-caught animals (P<0.002). Among wild-caught animals, intron CpG methylation was negatively correlated with RSC-V1aR (P<0.0001). An HKA test shows an excess of polymorphism around the intron SNPs (P<0.01), a pattern consistent with balancing selection at these sites. Together our data suggest that trade-offs between intra-pair and extra-pair paternity drive balancing selection on the epigenetic regulation of avpr1a in a spatial memory circuit.
